Been going thru tutorial 1 and getting an error at seciton 8 “Run Application”.
Error msg:
Exiting for exception: No acceptable implementations found in any libraries for “local.DemoProject.source”. Use log level 8 for more detail.
make: *** [run] Error 1^M
What is “log level 8”?
I saw from your previous topic that you asked about supported Vivado version.
What operating system are you running? There’s a known Xilinx vendor tool issue with Ubuntu 18.04+ and
the xsim hdl simulator platform. In this occasion you need to install Xilinx Vivado 2020.1+ to properly execute xsim.
As far as log level 8. When using OpenCPI command line utilities you can increase the logging level. You can accomplish this by using the environment variable OCPI_LOG_LEVEL . By increasing the log level it will give you more verbose logs.
For example in Tutorial 1 Section 8 you can invoke it using:
OCPI_LOG_LEVEL=8 ocpidev run application DemoApp.xml
Or alternatively you can export it in your environment to persist between executions like this:
export OCPI_LOG_LEVEL=8
Log level 8 is high, but you can even go a step higher to log level 10. IIRC default it 5 or 6.
That error message can point to two main issues IMO:
OCPI_LIBRARY_PATH.ocpidev run is used.What operating system are you running? There’s a known Xilinx vendor tool issue with Ubuntu 18.04+ and the xsim hdl simulator platform. In this occasion you need to install Xilinx Vivado 2020.1+ to properly execute xsim.
A bad combo of operating system should manifest a problem during build; I doubt that is the cause of this.
You’re right , I missed the “No acceptable implementations.”, part from the OP Which is usually leads to an issue withOCPI_LIBRARY_PATH.
From what I remember though when it comes to bad combo of operating system and Vivado in this particular case was that it did build successfully but failed to run. If I have time, I’ll try to reproduce it.
# Here's the bash script I've been using to run the tutorial
# script basename used as ocpi projectname
#!/usr/bin/bash
if [ -z $1 ]
then
/usr/bin/script $0.log /usr/bin/bash -c "$0 foo"
exit 0
fi
set -x
proj=$(basename $0 .sh)
here=$(dirname $(realpath $0))
projdir=$here/$proj
: --------------------------------------------------
: Show Platforms
: --------------------------------------------------
ocpidev show hdl platforms
: --------------------------------------------------
: 2 Create Project
: --------------------------------------------------
cd $here
ocpidev unregister project $proj
rm -rf $proj
ocpidev create project $proj --register
ocpidev show projects
tree $proj
: --------------------------------------------------
: 3 Create Component Library
: --------------------------------------------------
echo $projdir
cd $projdir
ocpidev create library components
tree
: --------------------------------------------------
: 4 Create Components
: --------------------------------------------------
cd $projdir/components
ocpidev create component source
ocpidev create component ramp
ocpidev create component square
ocpidev create component ander
tree
spec=./source.comp/source-spec.xml
sed -i 's/<\/ComponentSpec>/<!-- removed -->/g' $spec
cat >> $spec <<EOF
<Property name="value" initial="true" type="short" />
<Property name="nsamples" initial="true" />
<Port name="out" Producer="true" Protocol="rstream_protocol" />
</ComponentSpec>
EOF
spec=./ramp.comp/ramp-spec.xml
sed -i 's/<\/ComponentSpec>/<!-- removed -->/g' $spec
cat >> $spec <<EOF
<Port name="in" Producer="false" Protocol="rstream_protocol" />
<Port name="out" Producer="true" Protocol="rstream_protocol" />
</ComponentSpec>
EOF
spec=./square.comp/square-spec.xml
sed -i 's/<\/ComponentSpec>/<!-- removed -->/g' $spec
cat >> $spec <<EOF
<Port name="out" Producer="true" Protocol="rstream_protocol" />
</ComponentSpec>
EOF
spec=./ander.comp/ander-spec.xml
sed -i 's/<\/ComponentSpec>/<!-- removed -->/g' $spec
cat >> $spec <<EOF
<Port name="in1" Producer="false" Protocol="rstream_protocol" />
<Port name="in2" Producer="false" Protocol="rstream_protocol" />
<Port name="out" Producer="true" Protocol="iqstream_protocol" />
</ComponentSpec>
EOF
: --------------------------------------------------
: 5 Create Workers
: --------------------------------------------------
cd $projdir/components
ocpidev create worker source.rcc
ocpidev create worker ramp.hdl
ocpidev create worker square.hdl
ocpidev create worker ander.hdl
ocpidev show workers
xml=./ramp.hdl/ramp.xml
sed -i 's/\/>/>/g' $xml
sed -i 's/<\/HdlWorker>/<!-- removed -->/g' $xml
cat >> $xml <<EOF
<StreamInterface name="in" Datawidth="16"/>
<StreamInterface name="out" Datawidth="16" InsertEOM="true"/>
</HdlWorker>
EOF
xml=./square.hdl/square.xml
sed -i 's/\/>/>/g' $xml
sed -i 's/<\/HdlWorker>/<!-- removed -->/g' $xml
cat >> $xml <<EOF
<StreamInterface name="out" Datawidth="16" InsertEOM="true"/>
</HdlWorker>
EOF
xml=./ander.hdl/ander.xml
sed -i 's/\/>/>/g' $xml
sed -i 's/<\/HdlWorker>/<!-- removed -->/g' $xml
cat >> $xml <<EOF
<StreamInterface name="in1" Datawidth="16"/>
<StreamInterface name="in2" Datawidth="16"/>
<StreamInterface name="out" Datawidth="32" InsertEOM="true"/>
</HdlWorker>
EOF
rcc=./source.rcc/source.cc
sed -i 's/^/\/\//g' $rcc
cat >> $rcc <<EOF
#include "source-worker.hh"
using namespace OCPI::RCC;
using namespace SourceWorkerTypes;
class SourceWorker : public SourceWorkerBase {
size_t samples;
public:
SourceWorker() : samples(0) {}
RCCResult run(bool /*timedout*/) {
size_t n = std::min(out.data().real().capacity(),
properties().nsamples - samples);
if (n) {
out.data().real().resize(n);
samples += n;
for (int16_t *p = out.data().real().data(); n--; *p++ = properties().value) ;
return RCC_ADVANCE;
}
out.setEOF();
return RCC_ADVANCE_DONE;
}
};
SOURCE_START_INFO
SOURCE_END_INFO
EOF
vhd=./ramp.hdl/ramp.vhd
sed -i 's/^/--/g' $vhd
cat >> $vhd <<EOF
architecture rtl of worker is
signal do_work : bool_t;
signal out_data_i, buff_data : std_logic_vector(15 downto 0);
begin
-- When we are allowed to process data:
do_work <= out_in.ready and in_in.valid;
-- Outputs:
in_out.take <= do_work;
out_out.valid <= do_work;
out_data_i <= std_logic_vector(signed(in_in.data)
+ signed(buff_data));
out_out.data <= out_data_i;
-- Initialize or save off previous value when valid:
ramp : process(ctl_in.clk)
begin
if rising_edge(ctl_in.clk) then
if ctl_in.reset = '1' then
buff_data <= (others => '0');
elsif its(do_work) then
buff_data <= out_data_i;
end if;
end if;
end process ramp;
end rtl;
EOF
sed -i 's/^--\s*library/library/ig' $vhd
vhd=./square.hdl/square.vhd
sed -i 's/^/--/g' $vhd
cat >> $vhd <<EOF
architecture rtl of worker is
signal do_work : bool_t;
signal cnt : unsigned(7 downto 0);
begin
-- When we are allowed to process data:
do_work <= out_in.ready;
-- Outputs:
out_out.data <= (others => '1') when cnt < 32 else
(others => '0');
out_out.valid <= do_work;
-- Generate the square pulse's counter
square : process(ctl_in.clk)
begin
if rising_edge(ctl_in.clk) then
if ctl_in.reset = '1' then
cnt <= (others => '0');
elsif its(do_work) then -- advance when we are pushing
cnt <= cnt + 1;
if cnt = 63 then cnt <= (others => '0'); end if;
end if;
end if;
end process square;
end rtl;
EOF
sed -i 's/^--\s*library/library/ig' $vhd
vhd=./ander.hdl/ander.vhd
sed -i 's/^/--/g' $vhd
cat >> $vhd <<EOF
architecture rtl of worker is
signal do_work : bool_t;
begin
-- When we are allowed to process:
do_work <= out_in.ready and in1_in.valid and in2_in.valid;
-- Outputs:
in1_out.take <= do_work;
in2_out.take <= do_work;
out_out.valid <= do_work;
out_out.data(15 downto 0) <= in1_in.data and in2_in.data;
out_out.data(31 downto 16) <= in1_in.data;
end rtl;
EOF
sed -i 's/^--\s*library/library/ig' $vhd
ocpidev build library components --hdl-platform xsim
: --------------------------------------------------
: 6 Create HDL Assembly
: --------------------------------------------------
cd $projdir
ocpidev create hdl assembly demo_assembly
xml=$projdir/hdl/assemblies/demo_assembly/demo_assembly.xml
sed -i 's/<\/HdlAssembly>//g' $xml
cat >> $xml <<EOF
<Instance Worker="ramp" externals="true" />
<Instance Worker="square" />
<Instance Worker="ander" externals="true" />
<Connection>
<Port Instance="ramp" Name="out" />
<Port Instance="ander" Name="in1" />
</Connection>
<Connection>
<Port Instance="square" Name="out" />
<Port Instance="ander" Name="in2" />
</Connection>
</HdlAssembly>
EOF
ocpidev build hdl assembly demo_assembly --hdl-platform xsim
: --------------------------------------------------
: 7 Create Application
: --------------------------------------------------
ocpidev -X create application DemoApp
xml=$projdir/applications/DemoApp.xml
cat > $xml <<EOF
<Application package='local.DemoProject' finished='file_write'>
<Instance Component="source" Connect='ramp'>
<property name="value" value="128"/>
<property name="nsamples" value="2000"/>
</Instance>
<Instance Component="ramp"/>
<Instance Component="square"/>
<Instance Component="ander" Connect="file_write"/>
<Instance Component="ocpi.core.file_write">
<Property Name="fileName" Value="output_file.bin"/>
</Instance>
<Connection>
<Port Instance="ramp" Name="out"/>
<Port Instance="ander" Name="in1"/>
</Connection>
<Connection>
<Port Instance="square" Name="out"/>
<Port Instance="ander" Name="in2"/>
</Connection>
</Application>
EOF
# Why doesn't the application reference the assembly?
: --------------------------------------------------
: 8 Run Application
: --------------------------------------------------
cd $projdir
ocpidev run application DemoApp.xml
Using Centos7 …
Thanks - I’ll try looking the detailed log level.
I’ve added a script in case anyone is curious to try.
How did you run install the xsim platform?
I used the --minimal flag (ocpiadmin install platform xsim --minimal) when installing the platform in my environment.
The --minimal flag only builds the workers needed to build the testbias hdl assembly. If you do not provide it this flag it will build all the workers and all of the possible build configurations for that worker and will take a considerable more amount of time. You just have to remember to add --workers-as-needed when building future assemblies.
When I executed your script on CentOS7 using Xilinx Vivado 2019.2 I saw this in the “Create HDL Assembly” phase of your script.
++ : --------------------------------------------------
++ : 6 Create HDL Assembly
++ : --------------------------------------------------
++ cd /opencpi/projects/tutorial1
++ ocpidev create hdl assembly demo_assembly
++ xml=/opencpi/projects/tutorial1/hdl/assemblies/demo_assembly/demo_assembly.xml
++ sed -i 's/<\/HdlAssembly>//g' /opencpi/projects/tutorial1/hdl/assemblies/demo_assembly/demo_assembly.xml
++ cat
++ ocpidev build hdl assembly demo_assembly --hdl-platform xsim
Generating the definition file: gen/demo_assembly-defs.vh
Generating the implementation header file: gen/demo_assembly-impl.vh from demo_assembly.xml
Generating the implementation skeleton file: gen/demo_assembly-skel.v
Generating the assembly source file: gen/demo_assembly-assy.v from demo_assembly.xml
Generating the opposite language definition file: gen/demo_assembly-defs.vhd
Generating the VHDL constants file for config 0: target-xsim/generics.vhd
Generating the vhdl implementation file: gen/demo_assembly-impl.vhd from demo_assembly.xml
Generating the Verilog constants file for config 0: target-xsim/generics.vh
Building the demo_assembly assembly for xsim (target-xsim/demo_assembly) 0:(demo_assembly_ocpi_debug=false demo_assembly_ocpi_endian=little demo_assembly_ocpi_max_opcode_in=0 demo_assembly_ocpi_max_latency_out=256 demo_assembly_ocpi_max_bytes_in=8192 demo_assembly_ocpi_max_bytes_out=8192 demo_assembly_ocpi_max_opcode_out=0)
Tool "xsim" for target "xsim" succeeded. 0:09.89 at 15:05:10
Creating link to export worker binary: lib/hdl/xsim/demo_assembly -> target-xsim/demo_assembly
Creating link from lib/hdl/xsim/demo_assembly.cores -> target-xsim/demo_assembly.cores to expose the list of core dependencies for worker demo_assembly.
Creating link from lib/hdl/xsim/demo_assembly-generics.vhd -> target-xsim/generics.vhd to expose generics for worker demo_assembly.
Creating link from lib/hdl/xsim/demo_assembly.v -> target-xsim/demo_assembly-defs.vh to expose the definition of worker demo_assembly.
Creating link from lib/hdl/xsim/demo_assembly.vhd -> target-xsim/demo_assembly-defs.vhd to expose the other-language stub for worker demo_assembly.
Creating link from lib/hdl -> demo_assembly.xml to expose the demo_assembly implementation xml.
Error: HDL worker "wsi_width_clock_adapter" found in component library "/opencpi/projects/tutorial1/imports/ocpi.core/exports/lib/adapters" (/opencpi/projects/core/hdl/adapters/lib), but build config "9" not built for target "xsim"
/opencpi/cdk/include/hdl/hdl-lib2.mk:54: *** . Stop.
make: *** [container-demo_assembly_xsim_base/target-xsim/demo_assembly_xsim_base.bitz] Error 2
If you add --workers-as-needed to line 261
ocpidev build hdl assembly demo_assembly --hdl-platform xsim --workers-as-needed
It will successfully build the assembly
Additionally in the application package attribute needs to be updated to the project name.
Here are the changes I made to your script:
--- orig 2023-10-31 11:37:14.199593581 -0500
+++ mod 2023-10-31 11:37:17.791593463 -0500
@@ -258,7 +258,7 @@
</HdlAssembly>
EOF
-ocpidev build hdl assembly demo_assembly --hdl-platform xsim
+ocpidev build hdl assembly demo_assembly --hdl-platform xsim --workers-as-needed
: --------------------------------------------------
: 7 Create Application
@@ -268,7 +268,7 @@
xml=$projdir/applications/DemoApp.xml
cat > $xml <<EOF
-<Application package='local.DemoProject' finished='file_write'>
+<Application package='local.$proj' finished='file_write'>
<Instance Component="source" Connect='ramp'>
<property name="value" value="128"/>
<property name="nsamples" value="2000"/>
When the application executes it looks at the artifacts directories for artifacts described by the OpenCPI Application Specifiation (OAS) the directories it searches in is dictated by OCPI_LIBRARY_PATH environment variable. When using ocpidev run it figures out this path based on the project registry, so you don’t have to manually set it.
It goes through each artifact and tries to find match component specified in the app to the workers implemented for the available containers at runtime. “No Implementation was found” indicates that it could not satisfy the OAS for that particular worker. In this case the HDL assembly that contained the HDL workers didn’t exist because of the build failure.
Hi,
Doh! That would do it… “DemoProject” vs “DemoProject1”… my brain glossed over the 1…
btw I did the full build for xsim… (it did take a while!). Did not see that error for the wsi_width worker iirc… I added the ‘workers-as-needed’ flag anyway.
Anyways, now the tutorial advances a little further…
New Error: “Cannot obtain a local IP address. No socket interface found with usable address…”
Are you still on tutorial 1? Looks like you might have remnants of tutorial 10. What does your environment look like?
env | grep OCPI_
OCPI_TOOL_PLATFORM=centos7
OCPI_PREREQUISITES_DIR=/tools/opencpi/prerequisites
OCPI_TOOL_OS_VERSION=c7
OCPI_CDK_DIR=/tools/opencpi/cdk
OCPI_ROOT_DIR=/tools/opencpi
OCPI_TOOL_OS=linux
OCPI_TOOL_PLATFORM_DIR=/tools/opencpi/project-registry/ocpi.core/exports/rcc/platforms/centos7
OCPI_TOOL_ARCH=x86_64
OCPI_TOOL_DIR=centos7
No, haven’t played with Tut 10 yet.
Socket/IP error is from the Tut 1 script with the fixes.
Hmm. Are you running this in a container or virtualization? Does this machine have any network interfaces?
Working now - Tutorial passes.!
Yes, vmware on Win11 host.
The IP/socket error was happening when the host was on a another network.
The VM was not configured correctly for that network come to think of it, so I’ll hand wave and chaulk it up to that. Error went away with host/VM connected to its normal network.
Thanks!