I have successfully run through the example now. I would like to ask about the source running on the cpu, and the hdl workers such as ander, ramp, square, etc. are generated as bitstreams through assembly. Is the source data generated on the cpu transmitted to the fpga through the built-in communication component of opencpi for data exchange?
CPU
For the CPU , each worker gets compiled into to a .so file. This shared object gets loaded at runtime by the application when requested. At runtime you can specify what container to run on , so you can target a specific worker to run on the ARM and another worker to run on x86/64 and distribute your application across multiple platforms.
FPGA
For the FPGA, the assembly gets built into a container which becomes the bitstream to be loaded. Depending on the device you are using, we’ll use Zynq/ZynqUltrascale devices as an example. Within OpenCPI’s loadable kernel module, it can access the FPGA manager resources and load the bitstream at runtime.
The overall idea is that the entire bitstream is reloadable. When running different applications a new bitstream will be loaded on to the FPGA.
OpenCPI Artifacts
Each built OpenCPI artifact (CPU or FPGA) is embedded with a XML describing what is contained in that artifact. The runtime environment uses this knowledge to match artifacts with what is requested in the OpenCPI Application Specification (OAS) . Once all components are matched with their implementation artifacts, they get loaded and execution begins with those artifacts. The OCPI_LIBRARY_PATH environment variable is how you let the runtime environment know where to search for artifacts.
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