We’re considering a project where the connection between a RCC container and a HDL one would be a PCIe backplane and looking into the feasibility.
Is this still valid at version 2.x and above? I can see old support in ML605, ALST4, ZC706 and PicoEVB platforms but I think they’re all using uNOC. Was that bus common between control and data planes? Is it feasible that a PCIe to AXI Xilinx IP block with a PCIe hard IP block would be able to support both control and data planes now, or does it require two connections (or a PCIe for data plane plus ethernet from control plane)?
Is there a better research start point somewhere, or documentation on uNOC and SDP?