DMA Cache Mode on aarch64

OSP Development
1

Does anyone know why DMA cache use is disabled by default on aarch64?

In XferDma.cc (code) there is a comment saying “zynq-ultra caching does not work yet”, and the code forces the default DMA mode to uncached.

There isn’t any explanation as to what might be wrong with using the DMA in cached mode and on other architectures (aarch32) it’s defaulted to on.

Cached DMA can provide a big speed up in dataplane transfers, I’m going to have a go at fixing/validating it, just wondering if the cause of the problem is known.

Thanks

2

In all honesty we ran out of time during the initial effort and never went back to complete the implementation. Since we have had a working implementation we never spent the time to complete the job.

3

ok, so is there some configuration or code missing from the current implementation? or is there a decent chance it just works but hasn’t been validated?

4

I’d have to take a look at it again but if I had to guess there is probably some code missing to match the specifics in Zynq Ultra scale architecture.

5

ok, no worries, i’ll give it a go and see what happens.

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