I am looking at the feasibility of an OpenCPI application where sync between transmit and receive is deterministic. I have developed something similar using the UHD/RFNoC framework; where time_spec is given to a Tx stream, and then gating applied at the radio block against the master clock.
In OpenCPI - clearly the csts interface is designed to allow a similar timestamp to be streamed; but on the Tx side of the radio I was struggling to see whether anything gates this on the DRC by default. I couldn’t see an obvious TimeInterface in the likes of the AD9361 device workers… have I missed where this is done, or is it only accomplished by adding in something like the timegate_csts component, prior to entry into the DRC Tx Chain? If so, is some clock cycle determinism possibly lost due to the multiple FIFOs along this chain?