ANTSDR e310 OSP

OSP Development
1

This documents the journey from getting a Zynq7020+AD936x based device up and running with OpenCPI by creating and OpenCPI System Support Project (OSP) for it.

This quick run through uses the following versions:
OS: Ubuntu 24.04 or Ubuntu 22.04
OpenCPI: v2.4.8 or v2.4.9
Xilinx Vivado: 2024.1
Xilinx PetaLinux: 2024.1

Target Hardware - ANTSDR E310 - (HAM Geek Clone)

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Specifications:

  • Brand: HAMGEEK
  • Model: E310
  • RFIC: AD9361 for ADI. Frequency 70M~6G (A9361). Up to 56M instantaneous bandwidth (AD9361)
  • Number of channels: 2T2R MIMO
  • Baseband processing: ZYNQ7020, dual core for ARM, Cortex-A9 1G Byte DDR3 RAM. 256Mbit QSPI
  • Baseband processor: ZYNQ XC7Z020
  • Interfaces: one Giga ETH, one USB 2.0, Type C USB-JTAG and USB-UART, and GPIO expansion
  • Synchronization: External 10M, PPS inputs
  • Clock: VCTCXO with an initial accuracy of 0.5ppm. Dynamically adjusted clock via digital PLL. The accuracy can be better than +/-5ppb
  • API: For ADI IO (pre-installed), C/C++, and Python
  • Dimensions: Board: 100mm x 60mm/3.9" x 2.4"; case: 107.5mm x 64.5mm x 23mm / 4.2" x 2.5" x 0.9"
  • Power supply: USB TYPE-C powered
  • Transmit power: 3dBm (depends on frequency)
  • ADC: 12bit 61.44MS/s
  • DAC: 12bit 61.44MS/s
  • Noise figure: < 8db
  • Power consumption: 2~6W
  • Transmit IQ bandwidth: 10MSPS
  • Host interface: 1G ETH
  • GPS: None
  • External synchronized clock: 10M/PPS
  • Features: Hobbyist development, DIY, and open source code

Schematic

One of the crucial pieces of information you will need to create the OSP is the device’s schematic: Which can be found here.

Create HDF Files

A vivado hardware description file is a container that contains all the necessary information needed to build the correct boot artifacts.

  1. Open Vivado 2024.1
  2. Create Vivado Project
  3. Select Correct Part Number (xc7z020clg400-2)
  4. Create Block Design (design_1)
  5. Add ZYNQ7 Processing System Block
  6. Run Block Automation

From this point on follow this detailed guide on what needs to be done in the block design: Zynq HDF Creation Guide

Essentially you’ll take the schematic (Banks 50x) for the board configure the Zynq Processing System and do the following:

  • Ensure MIO pins match locations on the board
  • Add external ports to the 100MHz clock into the FPGA fabric to feed the control plane and data plane
  • Add external ports to access AXI control plane and data plane and make sure they are configured properly.

You should end of with a BD that looks like this:

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At this stage you are ready to export HDF File for PetaLinux.

File → Export → Hardware

Configure Petalinux

These are the minimum settings you need for the xilinx24_1_aarch32 platform to be compatible with this device.

  1. Source petalinux settings
  2. Create petalinux project using template
    petalinux-create --type project --template zynq --name plx-ant-e310-minimal
  3. cd into plx-ant-e310-minimal
  4. Point to the HDF file created in the previous step
    petalinux-config --get-hw-description= point it to the xsa

A window will pop up make the following modification:

DTG Settings → Kernel Bootargs → Add extra boot args
Add clk_ignore_unused

exit & save

The bootarg added above ensures that the 100MHz is enabled.

  1. Modify the rootfs
    petalinux-config -c rootfs

Image Features → debug tweaks
debug-tweaks
empty-root-password
serial-autologin-root

  1. Build the petalinux project
    petalinux-build
  2. Generate boot artifacts
    petalinux-package --boot --uboot --fsbl

Under images directory you should now have image.ub, boot.scr, BOOT.BIN
These make up the files in the releases tar that boots the device into Linux.

  1. Create release .xz

Name directory 2024.1-<platform_name>-release
tar -cJf 2024.1-<platform_name>-release.xz 2024.1-<platform_name>-release

Release Artifact for a310: Prebuilt Release

Create initial OSP

First thing we want to do is be able to get hardware acceleration working. This is accomplished by building and running the testbias.xml assembly and application.

  1. Create OSP Project ocpidev create project
  2. Create directories hdl/platforms/a310
  3. Modeled OSP off existing Zynq platforms. This is mostly a copy & paste exercise with some name changes.

* note: Zynq Ultrascale based platforms have additional kernel & rootfs configuration that differ from this platform. I plan on creating a similar run through in the future.

Add AD936x Support

First question to answer is whether the platform supports the CMOS or LVDS interface on the AD936x?
Similar exercise as hardware accelerate, use the E310/PlutoSDR as CMOS the reference or zed+fmcomms for LVDS. After comparing the pinouts it was evident that this device matched exactly libresdr platform.

The DRC from examples project works, a new one will be needed to correctly switch the RF switch > 3Ghz but I was able to verify TX capability.

The a310 OSP still needs some polishing but it is located here: Aaron Olivarez / ANTSDR · GitLab