Introduction
I’ve had some questions recently relating to the use of Xilinx Integrated Logic Analyzers inside OpenCPI HDL Workers.
I’m writing this as a current summary of what I understand on this topic. Worth noting, I do not have specific experience in use of Xilinx ILA, so I will be referring to what guidance is already available in various places, and using this forum post as a sign post to that.
If you have experience using ILA (or the non-Xilinx equivalents), and want to provide some additional advice, please feel free to reply to this post.
Current Primary Guidance
The primary guidance available relating to integration of ILAs is in the Debugging Tools Guide.
Section 3.1 provides two slightly different use cases on integrating an ILA core.
Warning
The guidance in Section 3.1 was written for Xilinx Vivado 2017.1.
There is an open issue on Gitlab that provides some further guidance on additional steps that are needed in newer versions of Xilinx Vivado (certainly 2018.3+).
This open issue links to a closed issue which contains a screen recording showing some of these steps in action.
Other sections of the document address Xilinx ISE and Altera SignalTap II.
Considerations for Specific Platforms
E310
The serial port on the external case of an E310 does not expose the JTAG connection to the FPGA.
If you wish to use an ILA with an E310, you will need to gain access to the internal connector to drive the JTAG port.
Note
I am informed that this internal connector is non-standard, but have not personally seen it.
The JTAG connector is soldered onto the board to a 3x2 1mm header. Using this will require soldering and a modified ribbon cable.
This will require removing the external casing of the E310, which you do so at your own risk.